L'effet du degré de réseau d'interconnexion multi-étages sur ses performances: le cas des réseaux Delta et réseaux Delta surdimensionnés

Lors de la construction d'un ordinateur paralléle, le réseau d'interconnexion ainsi que ses performances sont des facteurs cruciaux à étudier. Aujourd'hui, la technologie supporte la construction de crossbars de taille limitée (jusqu'à 128). Pour des machines avec un plus grands nombre de points de connexion, ces crossbars peuvent être utilisés comme éléments de commutation de réseaux d'interconnexion multi-étages. En fait, un réseau d'interconnexion est défini par sa topologie, son algorithme d'acheminement, sa stratégie de commutation et son mécanisme de contrôle de flux. Un des facteurs définis par la topologie est le degré. Le degré d'un réseau d'interconnexion multi-étages est la taille des commutateurs qui le composent. Dans ce papier, nous étudions l'effet de la taille du commutateur sur les performances de deux classes de réseaux d'interconnexion multi-étages: les fameux réseaux Delta et une sous-classe de cette famille qui s'appelle les réseaux Delta surdimensionnés. Cette étude initie une réflexion sur l'utilisation des réseaux d'interconnexion multi-étages dans les machines SMP actuelles

A Modeling Approach based on UML/MARTE for GPU Architecture

Nowadays, the High Performance Computing is part of the context of embedded systems. Graphics Processing Units (GPUs) are more and more used in acceleration of the most part of algorithms and applications. Over the past years, not many efforts have been done to describe abstractions of applications in relation to their target architectures. Thus, when developers need to associate applications and GPUs, for example, they find difficulty and prefer using API for these architectures. This paper presents a metamodel extension for MARTE profile and a model for GPU architectures. The main goal is to specify the task and data allocation in the memory hierarchy of these architectures. The results show that this approach will help to generate code for GPUs based on model transformations using Model Driven Engineering (MDE).Comment: Symposium en Architectures nouvelles de machines (SympA'14) (2011

Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems

International audiencePartial and dynamic reconfiguration provides a relevant new dimension to design efficient parallel embedded systems. However, due to the encasing complexity of such systems, ensuring the consistency and parallelism management at runtime is still a key challenge. So architecture models and design methodology are required to allow for efficient component reuse and hardware reconfiguration management.This paper presents a distributed persistence management model and its implementation for reconfigurable multiprocessor systems on dynamically reconfigurable circuits. The proposed approach is inspired from the well-known component based models used in software applications development. Our model is based on membranes wrapping the systems components. The objective is to improve design productivity and ensure consistency by managing context switching and storage using modular distributed hardware controllers. These membranes are distributed and optimized with the aim to design self-adaptive systems by allowing dynamic changes in parallelism degree and contexts migration. Simulation and synthesis results are given to show performances and effectiveness of our methodology

Semi-distributed control for FPGA-based reconfigurable systems

Conférence DSD TurquieDue to the growing complexity of the applications targeted by FPGA-based reconfigurable systems, the control design of such systems is becoming one of the main hurdles faced by designers. In this paper, we propose a semi-distributed control model based on the separation between different control concerns (monitoring, decision-making and reconfiguration) and on formalism-oriented design in order to decrease the design complexity of the control, and facilitate design verification, reuse and scalability. This model is composed of distributed controllers handling each the self-adaptivity of a reconfigurable region of the system, and a coordinator that coordinates their reconfiguration decisions in order to respect global system constraints. Implementations on FPGA showed that our semi-distributed control model is more flexible, reusable and scalable than the centralized one, at the cost of a slight increase in required hardware resources

Separating Control and Data Flow: Methodology and Automotive System Case Study

In this document we propose to study the control/data flow separation design methodology, using Scade and Mode-Automata, and its application in the design of an automotive system. This methodology allows to facilitate the specification of different kinds of systems and to have a better readability. It also separates the study of the different parts by using the most appropriate existing tools for each of them. To do that, we study a cruise control system with GPS which makes possible the control of a car speed depending on its position given by a GPS. This system combines both control and data processing and can be specified using our methodology. The goal of this work consists in presenting the application of our methodology on a real system and studing its advantages notably for formal verification

High level modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE

International audienceSystem-on-Chip (SoC) architectures are becoming the preferred solution for implementing modern embedded systems. However their design complexity continues to augment due to the increase in integrated hardware resources requiring new design methodologies and tools. In this paper we present a novel SoC co-design methodology based on aModel Driven Engineering framework while utilizing the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology permits us to model fine grain reconfigurable architectures such as FPGAs and allows to extend the standard for integrating new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The overall objective is to carry out modeling at a high abstraction level expressed in a graphical language like UML (Unified Modeling Language) and afterwards transformations of these models, automatically generate the necessary specifications required for FPGA implementation

Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs

International audienceThe number of integrated transistors that can be contained on a chip are increasing at an exponential rate, along with rise in targeted sophisticated applications. Thus the design of Systems-on-Chip (SoC) is becoming more and more complex. Hence there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. This paper presents a novel approach for expressing system adaptivity and reconfigurability in Gaspard, a SoC co-design framework, with special focus on partially dynamically reconfigurable FPGAs. The framework is compliant with UML MARTE profile proposed by Object Management Group, for modeling and analysis of realtime embedded systems. The overall objective is to carry out system modeling at a high abstraction level expressed in UML; and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesi

Model Driven Engineering Benefits for High Level Synthesis

This report presents the benefits of using the Model Driven Engineering (MDE) methodology to solve major difficulties encountered by usual high level synthesis (HLS) flows. These advantages are highlighted in a design space exploration environment we propose. MDE is the skeleton of our HLS flow dedicated to intensive signal processing to demonstrate the expected benefits of these software technologies extended to hardware design. Both users and designers of the design flow benefit from the MDE methodology, participating to a concrete and effective advancement in the high level synthesis research domain. The flow is automatized from UML specifications to VHDL code generation and has been successfully evaluated for the conception of a video processing application

MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs

International audienceAs System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation